표 4. | Table 4. 10-bit SAR ADC의 각 스위칭 구조별 성능지표 | Summary of performance on different switching schemes for a 10-bit SAR ADC.
Switching scheme | Average switching energy ( C V r e f 2 ) | Energy saving (%) | Area (c) | Area reduction (%) |
Conventional [1] | 1,363.3 | Ref | 211 | Ref |
Monotonic [2] | 255.5 | 81.26 | 210 | 50.00 |
HSRS [3] | 106.2 | 92.20 | 210 | 50.00 |
Vaq-based tri-level [4] | 48.03 | 96.48 | 28 | 87.50 |
Hybrid [5] | 15.88 | 98.83 | 29 | 75.00 |
Vcm-based [6] | 170.17 | 87.52 | 210 | 50.00 |
Proposed (M:1,N:8) | 26.542 | 98.05 | 29 | 75.00 |
Proposed (M:2,N:7) | 3.3022 | 99.76 | 28 | 87.50 |
Proposed (M:3,N:6) | 0.4089 | 99.97 | 27 | 93.75 |